Description
Improper mstatus.SUM bit retention (non-zero) in Open-Source RISC-V Processor commit f517abb violates privileged spec constraints, enabling potential physical memory access attacks.
Metrics
CVSS 3.1 9.1/10
CVSS:3.1/AV:N/AC:L/PR:N/UI:N/S:U/C:H/I:N/A:HWeakness enumeration
Affected software
No affected versions have been published.
Timeline
- Published
- Jul 1, 2025
- Last modified
- Jun 17, 2026
- NVD status
- Deferred