Description
In certain Arm CPUs, a CPP RCTX instruction executed on one Processing Element (PE) may inhibit TLB invalidation when a TLBI is issued to the PE, either by the same PE or another PE in the shareability domain. In this case, the PE may retain stale TLB entries which should have been invalidated by the TLBI.
Metrics
CVSS 3.1 7.9/10
CVSS:3.1/AV:L/AC:L/PR:H/UI:N/S:C/C:H/I:H/A:NWeakness enumeration
Affected software
| Vendor | Product | Versions |
|---|---|---|
| Arm | Neoverse-N2 | 0 |
| Arm | Neoverse-V3AE | 0 |
| Arm | Neoverse-V3 | 0 |
| Arm | Neoverse-V2 | 0 |
| Arm | Cortex-X925 | 0 |
| Arm | Cortex-X4 | 0 |
| Arm | Cortex-X3 | 0 |
| Arm | Cortex-X2 | 0 |
| Arm | Cortex-A710 | 0 |
| Arm | C1-Premium | 0 |
| Arm | C1-Ultra | 0 |
References
- https://developer.arm.com/documentation/111546Vendor Advisory
- https://graph.volerion.com/view?ID=CVE-2025-0647Third Party Advisory
Timeline
- Published
- Jan 14, 2026
- Last modified
- Jun 17, 2026
- NVD status
- Analyzed