Description
In the Linux kernel, the following vulnerability has been resolved:
spi: microchip-core: ensure TX and RX FIFOs are empty at start of a transfer
While transmitting with rx_len == 0, the RX FIFO is not going to be emptied in the interrupt handler. A subsequent transfer could then read crap from the previous transfer out of the RX FIFO into the start RX buffer. The core provides a register that will empty the RX and TX FIFOs, so do that before each transfer.
Metrics
CVSS 3.1 5.5/10
CVSS:3.1/AV:L/AC:L/PR:L/UI:N/S:U/C:N/I:N/A:HAffected software
| Vendor | Product | Versions |
|---|---|---|
| Linux | Linux | >= 9ac8d17694b66d54b13e9718b25c14ca36dbebbd, < 950375a0ba7d6c82ea5b5a44dd48a9e41fa45826; >= 9ac8d17694b66d54b13e9718b25c14ca36dbebbd, < 3feda3677e8bbe833c3a62a4091377a08f015b80; >= 9ac8d17694b66d54b13e9718b25c14ca36dbebbd, < 45e03d35229b680b79dfea1103a1f2f07d0b5d75; >= 9ac8d17694b66d54b13e9718b25c14ca36dbebbd, < 9cf71eb0faef4bff01df4264841b8465382d7927 |
| Linux | Linux | 6.0 |
References
- https://git.kernel.org/stable/c/3feda3677e8bbe833c3a62a4091377a08f015b80Patch
- https://git.kernel.org/stable/c/45e03d35229b680b79dfea1103a1f2f07d0b5d75Patch
- https://git.kernel.org/stable/c/950375a0ba7d6c82ea5b5a44dd48a9e41fa45826
- https://git.kernel.org/stable/c/9cf71eb0faef4bff01df4264841b8465382d7927Patch
Timeline
- Published
- Aug 17, 2024
- Last modified
- Oct 30, 2026
- NVD status
- Modified