Description
Incorrect behavior order in transition between executive monitor and SMI transfer monitor (STM) in some Intel(R) Processor may allow a privileged user to potentially enable escalation of privilege via local access.
Metrics
CVSS 3.1 7.2/10
CVSS:3.1/AV:L/AC:H/PR:H/UI:R/S:C/C:H/I:H/A:HWeakness enumeration
Affected software
No affected versions have been published.
Timeline
- Published
- Aug 14, 2024
- Last modified
- Jun 17, 2026
- NVD status
- Deferred