Description
Improper configuration in block design for Intel(R) MAX(R) 10 FPGA all versions may allow an authenticated user to potentially enable escalation of privilege and information disclosure via physical access.
Metrics
CVSS 3.1 5.9/10
CVSS:3.1/AV:P/AC:L/PR:L/UI:N/S:U/C:H/I:H/A:NAffected software
No affected versions have been published.
Timeline
- Published
- Mar 12, 2020
- Last modified
- Jun 17, 2026
- NVD status
- Modified